Optical and analog AI compute: what survives measurement

Only in narrow corners. The optics-native inference cost model found a real latency win for batch-1 decode of a state-space model, but only with WDM microrings, small-to-mid width, about 5-bit precision and error-tolerant workloads; once a fused GPU removed launch overhead, 15–56× became single-digit×. The all-optical kernel study found near parity (1.23×) against a digital ASIC. Our claims register lists optical compute for inference as dead and optical interconnect as alive but bounded.

It depends on the sequence architecture. Analog in-memory compute accelerates static-weight matrix multiplies but cannot touch attention's growing KV cache, so on a transformer its decode advantage dilutes with context. The AIMC window papergives the design rule: the attention window policy, sliding versus full, not the attention fraction, decides whether a hybrid keeps the advantage. The claims register places AIMC's lane at power-bound 1–8B edge models plus power-capped prefill of up to about 8k tokens. Device-level work in the nonlinearity study found that analog nonlinearities match ReLU only after hardware-aware retraining, in a first-order model on MNIST. See the glossary entry on analog in-memory computing.

In moving data at scale, mostly in decode. The wrong phase traces the "50% of MoE prefill is networking" figure to blended sources and finds decode dominates inference communication. Its energy case is weak: under honest laser power and utilization, optical KV movement lost to board-level electrical links in the co-design synthesis. The surviving rationale is bandwidth density for pooled KV at rack reach and extreme scale. For the industry side, see our analyses of co-packaged optics after OCP 2026 and photonics for AI interconnect, and the glossary entry on co-packaged optics.

Each paper registered its predictions and kill criteria before running, and reports misses alongside survivors. Most rows above are cost-model or simulation results calibrated to published chips; for example, the optics-native model reproduces a 2025 coherent photonic chip's 1.28 TOPS throughput exactly. None is a measurement on a fabricated NeuroGenesys chip. The photonics-budget tool exposes four of the back-of-envelope gates.

• Paper • Falsification study • Jun 27, 2026Reverse-engineering a trained network for all-optical inference via random-feature kernelsCan inference on an already-trained network run entirely in light? An envelope exists, bounded by a quantified depth→width feature wall — and an honest requote against a digital ASIC collapses the headline speedup to near parity. Two genuine advantages survive: precision robustness and zero-forgetting frozen features.
• Paper • Cost-model study • Jun 27, 2026Where optics-native inference actually pays: a cost-model studySpeed-of-light inference is real but narrow and conditional: an optics-native state-space model beats a GPU on batch-1 decode latency only inside a tight box — WDM microrings, small-to-mid width, ~5-bit precision, error-tolerant workloads. The model reproduces a published 2025 chip's throughput exactly; the defensible contribution is the cost model itself.
• Paper • Synthesis • Jul 29, 2026What survived: a claims register with falsifiers for a pre-registered AI research programEvery surviving claim from a pre-registered, run-once program, with its evidence and its falsifier. Alive: pool-relative verifier exploitability, test-time recurrent depth, the AIMC window-policy rule, narrow optical interconnect. Dead: wave/complex substrates, optical compute for inference, frontier-datacenter AIMC, and the ε 'universality class'.
• Paper • Defensive publication • Jul 27, 2026Which sequence architecture keeps analog in-memory compute's advantage? A cost-model answer with a design ruleAnalog in-memory compute accelerates static-weight matmuls but cannot touch attention's growing KV cache, so its decode advantage dilutes with context length. The attention window policy — sliding vs. full — not the attention fraction, decides whether a hybrid keeps the advantage. Distilled from ~70 pre-registered falsification experiments.
• Paper • Synthesis • Jul 30, 2026Can analog or photonic hardware replace LLM inference silicon? AIMC for compute, optics for decode interconnectAbout 54 pre-registered experiments found no general replacement. Analog MoE routing adds no accuracy, and the FFN it accelerates is under 19% of decode energy. Optical interconnect's energy win collapses under honest laser power, leaving bandwidth density at extreme scale, mostly in decode.
• Paper • Synthesis • Jul 30, 2026The wrong phase: optical interconnect's case is in decode, not prefillA source-checked review found the 'networking is 50% of MoE prefill' figure blends training, decode, and an unsupported claim; measured prefill communication is 9–23%. Decode dominates communication, so that is where optical interconnect's case lives. Digital's move to native 4-bit also erodes the precision edge analog designs relied on.
• Paper • Falsification study • Jul 30, 2026The last hardware flank: analog prefill survives only as an energy-bound nicheFive pre-registered kill tests on analog in-memory prefill with optically disaggregated decode. Shipping the KV cache costs under 0.1% of prefill energy, demoting the optical claim; the cache survives 5 bits but collapses at 4. Against measured chips, digital wins throughput per area, leaving an energy-bound, short-prompt niche.
• Paper • Negative results • Aug 26, 2026The log-arithmetic gates: weight sharing buys compute, not storageEight prior-art reviews and six pre-registered experiments on log-domain neurons and the hardware proposed for them. None of the 16 ideas was new; LNS loses at inference precisions and analog log-domain error compounds with fan-in. The output is six design rules — chiefly, weight sharing pays only when the freed compute is spent.
• Paper • Falsification study • Sep 8, 2026The wavefield gate: Fourier modes are the wrong basis for visual computingA proposed photonic 'wavefield' graphics architecture, tested on its two measurable claims. Fourier modes need 21–49% of coefficients to reach 35 dB, not 0.5%, and a one-pixel move changes 97% of them. Display space–bandwidth and conversion costs close the rest: the physics is sound, the advantages are not.
• Paper • Falsification study • Aug 4, 2026Diamond is a material, not a system: no case for quantum memory in AI datacentersAn AI-written brief cast diamond as quantum memory between AI accelerators. The claim fails structurally: collectives copy data, superdense coding gives no net gain, and entanglement rates fall ~12.7 orders of magnitude short. Diamond's thermal conductivity holds up; its classical-electronics claims are overstated. Verification is partial and labeled as such.
• Paper • Research note • Jun 29, 2026Analog chips can do nonlinear ML — if you co-design around the device's native nonlinearityOn MNIST, a frozen MLP tolerates 4-bit weights with moderate device noise; 2-bit is the cliff. Saturating device nonlinearities match ReLU only after hardware-aware retraining (0.947 vs 0.938) — naive swaps fail. Class-IL routing stays robust at 4-bit with heavy noise. A first-order model, not a device simulation.