Can a guardian chip stop a learning model from forgetting? Only partly.
• 6 min read • By Models Team
Key findings
- In published methods that protect old knowledge, the protected model works as a forward-only reference during training: it scores drift, supplies targets, generates replay and checks updates.
- A frozen reference goes stale: in MIT's self-distillation work a frozen base teacher trained stably but underperformed a slowly updated copy, which itself drifts unless re-anchored.
- Digital inference ASICs are the only credible home for an LLM-scale guardian in 2026; Taalas HC1 is the only shipping chip whose weights cannot be rewritten, and it holds one 8B model.
- The largest analog Transformer in silicon has 7.1M weights and lost about 5% accuracy over 30 days from drift, which disqualifies it as the stable reference.
- No one has published a deployed guardian system, a false-veto rate, or an end-to-end cost measurement, and retention-preserving training can reinforce implanted backdoors.

A model that keeps learning after deployment will, sooner or later, overwrite something it used to know. One appealing fix is architectural: keep a separate, trusted core model on its own high-performance silicon, an inference ASIC or even a photonic processor, and let it guard the learner. We reviewed the continual-learning, hardware and security literature through November 2026 to see whether that design holds up. It can be built today, but the guardian looks less like a second brain and more like a slow, trusted reference with a narrow job.
Across the methods that protect old knowledge, the protected model is used forward-only during training. It measures how far the learner's outputs move from its own on new data, supplies distillation targets, generates synthetic replay of old knowledge, and checks proposed updates against a fixed answer set before they are kept. The cheapest drift signal is the KL divergence between the two models on the new inputs. In RL's Razor it predicted forgetting with R² = 0.96 on a toy benchmark, but only 0.71 in language models. Predicting which individual answers an update will break is weaker still: a 2026 study of five model-version updates found that detectors flagged answers flipping from correct to wrong with an AUROC of about 0.57–0.85 on knowledge and reasoning benchmarks, and as low as 0.42 on code. A guardian should therefore gate on aggregate thresholds over a test set, not on per-item predictions.
The guardian also cannot simply be frozen. In MIT's on-policy self-distillation work (ICML 2026), a frozen base teacher trained stably but underperformed, using the live model as its own teacher diverged, and a slowly updated copy worked best. On Qwen2.5-7B learning science Q&A, the average on prior abilities was 64.5 with that method against 53.4 for ordinary fine-tuning, from a starting point of 65.5. It cost about 2.5 times the compute and 4 times the wall-clock time. A September follow-up, iSDFT, found the slow copy drifts too and re-anchored it to the frozen base. The design that follows has three layers: an unchangeable original, a slow copy that updates only during offline consolidation, and the fast learner, with new facts held in removable external memory until they are checked.
That shapes the hardware case. Routine checks against a fixed test set barely need a guardian chip, because its answers can be computed once and cached. The recurring cost is generating replay and self-distillation text, which is decode-bound, the work fast inference chips were built for. By our estimate a same-size reference on GPUs adds about a third to training compute, and vendor efficiency claims of 5 to 35 times would cut that to a few percent. None of those claims has been independently checked. Taalas HC1 is the only shipping chip whose weights physically cannot be rewritten. It hardwires Llama 3.1 8B, and an independent measurement found 14,357 tokens per second against the company's figure of about 17,000. But it runs one model, at reduced 3- and 6-bit precision, and a drift measurement taken against a lossy copy measures drift from the copy. Large guardians need high-memory parts such as Google's TPU Ironwood, with 192 GB of HBM per chip. We found no public deployment in which a training cluster calls a dedicated inference chip as its reference model.
Photonics and analog compute fit the edges of the role, not the centre. Lightmatter's photonic processor, published in Nature in April 2025, ran ResNet and BERT unmodified while drawing 78 W of electrical power against 1.6 W of optical power, and heise reported just under 30% of conventional accuracy on natural-language questions. Its weights are loaded from ordinary digital memory, so a photonic core is only as protected as that memory. On the analog side, the largest Transformer run in silicon is an ALBERT model with 7.1M weights on phase-change memory, which lost about 5% accuracy over 30 days from conductance drift, under 1% with recalibration. For the one model meant to define what counts as forgetting, any drift of its own is disqualifying. Their realistic roles are small probe models and drift alarms checked against a digital master, and the optical links between learner and guardian.
The harder problems sit above the silicon. A guardian that protects what a model knows will fight legitimate corrections unless it knows which facts are meant to change. It also protects whatever is already there: about 250 poisoned documents were enough to backdoor models from 600M to 13B parameters, and P-Trojan showed backdoors can be reinforced by continual fine-tuning, including fine-tuning with anti-forgetting methods. Its security value lies in source-gated writes, revocable memory, a clean frozen root to compare against, and restoring snapshots rather than training forward.
Several of the key 2026 results are unreviewed preprints, and no benchmark yet scores how often a guardian wrongly blocks a good update or misses a bad one. Nor has anyone tested whether a small guardian, the size that fits a hardwired die or an analog chip, can protect a much larger learner. A dedicated chip makes it cheap and tamper-resistant to ask whether a model has drifted from what it knew. It cannot decide whether that drift was a mistake, a correction or an attack, and that judgment is the part still to build.
Sources
- RL's Razor: Why Online Reinforcement Learning Forgets Less — arXiv:2509.04259, ICLR 2026
- No Universal Signal Predicts Sample-Level LLM Regression under Version Updates — arXiv:2608.13607, August 2026
- Self-Distillation Enables Continual Learning — arXiv:2601.19897, ICML 2026
- iSDFT: Information-Proximal Self-Distillation for Continual Learning in LLMs — Hugging Face Papers 2609.24646, September 2026
- AI inference cast in silicon: Taalas announces HC1 chip — heise online, 2026
- Taalas HC1: Hardwiring Llama 3.1 Into Silicon for 17,000 Tokens/Second — NYU Shanghai RITS, 2026
- TPU7x (Ironwood) — Google Cloud documentation
- Photonic computer chips perform as well as purely electronic counterparts, say researchers — Physics World, April 2025
- First light processors operate AI efficiently — heise online, April 2025
- Demonstration of transformer-based ALBERT model on a 14nm analog AI inference chip — Nature Communications, 2025
- A small number of samples can poison LLMs — Anthropic, UK AISI and Alan Turing Institute, October 2025
- Persistent Backdoor Attacks under Continual Fine-Tuning of LLMs — arXiv:2512.14741, December 2025
Related research
- Research Desk • Machine LearningTo keep what a model knows, control what it is allowed to moveMeta cut forgetting from 89% to 11% by updating 500 memory slots. Across continual learning, the methods that hold up limit what moves and keep old data in play.
- Research Desk • Machine LearningA model rewrote another model's weights. Read what it took away.An MIT agent edited 0.016% of a small Qwen model and its math scores jumped. Across weight editing in 2026, subtraction works and addition still lags.
- Research Desk • SiliconA billion neurons in silicon: neuromorphic computing grows up.The brain runs general intelligence on twenty watts. Event-driven silicon is how the industry starts closing a five-order-of-magnitude gap.
- Publication • Continual LearningEscaping the saturated game: plasticity, harder benchmarks, and retrieval in continual learning
- Publication • Continual LearningCatastrophic forgetting in class-incremental learning is a verifier-exploitability problem
- Publication • Silicon & Analog ComputeWhich sequence architecture keeps analog in-memory compute's advantage? A cost-model answer with a design rule
Learn the background
- Academy • Efficient AI: Inference, Sparsity & HardwareBeyond the GPU: analog, photonic and in-memory compute
- Academy • Efficient AI: Inference, Sparsity & HardwareInference economics: KV caches, memory bandwidth and batching
- Research tool • In-browser · Pythonphotonics-budgetFour calculators from the log-arithmetic gates: the optical recirculation pass budget, the nonlinear material figure of merit, the logarithmic-number-system energy check, and why fixed pre-ADC aggregation collapses to one matrix.
